| 摘要 |
PROBLEM TO BE SOLVED: To solve problems of a conventional D/A converter wherein SNR is deteriorated due to generation of a new noise because of susceptibleness to jitter caused by increase in edges of an output signal and the configuration of a filter circuit 3 of a post-stage is complicated because of a large noise component still remained although the noise component around the fs is reduced. SOLUTION: When a level of a clock signal or an inverted clock signal received at a clock terminal 14 is an H level, potential generating sections 19 to 22 provided to a novel D/A converter generate potential sets in response to a level of a 1-bit signal received from a data terminal 13 or a 1-bit signal delayed by a delay circuit 15 and the potential sets generated from the potential generating sections 19 to 22 are composed. COPYRIGHT: (C)2004,JPO
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