发明名称 INTEGRATED CIRCUIT DESIGNING METHOD AND ITS PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide a standard cell and its replacing method capable of designing an integrated circuit whose power consumption is small in a short period without rearranging wiring. SOLUTION: A cell optimizing means performs an operation to replace a certain standard cell with a standard cell whose logical function, terminal position, terminal shape, and cell outer shape are the same as those of the standard cell, and whose power consumption is smaller in a part where the arrangement of cells and signal transmission delay in a wired circuit have a margin. A cell list storing part stores not only the standard cell to be used for designing an integrated circuit but also the proper number of standard cells whose logical functions, terminal positions, terminal shapes, and cell outer shapes are the same, and whose power consumption is smaller. Therefore, it is not necessary to perform the re-arrangement of the standard cells or rewriting accompanied with this while reducing power consumption, and it is possible to realize a short design period. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004126693(A) 申请公布日期 2004.04.22
申请号 JP20020286330 申请日期 2002.09.30
申请人 NEC CORP 发明人 ONO YOSHIHIRO
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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