| 摘要 |
A test-program generator capable of implementing a methodology, based on a formal language, for scheduling system-level transactions in generated test programs. A system to be tested may be composed of multiple processors, busses, bus-bridges, shared memories, etc. The scheduling methodology is based on an exploration of scheduling abilities in a hardware system and features a Hierarchical Scheduling Language for specifying transactions and their ordering. Through a grouping hierarchy, which may also be expressed in the form of an equivalent tree, the Hierarchical Scheduling Language combines the ability to stress related logical areas of the system with the possibility of applying high-level scheduling requests. A method for generating testcases based on request-files written in the Hierarchical Scheduling Language is also presented.
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