发明名称 |
Selectively processing different size data in multiplier and ALU paths in parallel |
摘要 |
An integrated circuit which has two separate paths for two different data widths. The first processing path processes data up to n bits in a n multiplier. A second path operates in parallel with the first path, and includes smaller units which process data up to n 2 bits. The two paths can operate in parallel, but since the two paths have different data widths, they can more effectively operate with the different data sizes. |
申请公布号 |
US6725360(B1) |
申请公布日期 |
2004.04.20 |
申请号 |
US20000541116 |
申请日期 |
2000.03.31 |
申请人 |
INTEL CORPORATION;ANALOG DEVICES, INC. |
发明人 |
ALDRICH BRADLEY C.;FRIDMAN JOSE;MEYER PAUL;LIANG GANG |
分类号 |
G06F7/50;G06F7/52;G06F7/57;G06F9/302;G06F15/78;(IPC1-7):G06F9/302 |
主分类号 |
G06F7/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|