发明名称 |
EEPROM and EEPROM manufacturing method |
摘要 |
A memory transistor of an EEPROM has a floating gate electrode of a shape such that it covers the entirety of a tunnel film and a channel region and does not cover a region between the channel region and an embedded layer. And, a control gate electrode is formed on an interlayer insulating film on the floating gate electrode into a shape such that it is wider than the floating gate electrode above the tunnel film, and is narrower than the floating gate electrode above the channel region.
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申请公布号 |
US2004070022(A1) |
申请公布日期 |
2004.04.15 |
申请号 |
US20030660682 |
申请日期 |
2003.09.12 |
申请人 |
ITOU HIROYASU;KATADA MITSUTAKA;MURAMOTO HIDETOSHI |
发明人 |
ITOU HIROYASU;KATADA MITSUTAKA;MURAMOTO HIDETOSHI |
分类号 |
H01L21/8247;H01L27/115;H01L29/423;H01L29/788;H01L29/792;(IPC1-7):H01L29/76 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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