发明名称 |
SYSTEM AND METHOD FOR TRANSFERRING DATA AMONG TRANSCEIVERS SUBSTANTIALLY VOID OF DATA DEPENDENT JITTER |
摘要 |
A communication system, clock generation circuit, and method are provided for receiving jitter upon data and to generate a clock reference that does not contain the received jitter. The clock reference can be used either by a digital subsystem of a communication system node, or can be transmitted as substantially jitter-free data from that node to a downstream node of the communication system. Instead of recovering the clock reference from the data having jitter, a pattern is regularly defined within the data stream preferably at periodic, timed intervals. The data pattern may be made up of a series of non-transitions which, regardless of any jitter in the data itself, does not impute any jitter onto a phase-locked loop triggered from an edge of the non-transitioning data pattern. Using the edge as a reference point, a jitter-free clocking signal can be derived at the same frequency as a clocking signal which would normally be produced from the jitter-induced data. |
申请公布号 |
WO2004032409(A1) |
申请公布日期 |
2004.04.15 |
申请号 |
WO2003US30053 |
申请日期 |
2003.09.24 |
申请人 |
OASIS SILICON SYSTEMS, INC. |
发明人 |
KNAPP, DAVID, J.;LEWIS, JASON, E. |
分类号 |
H03L7/06;H03L7/07;H04L7/00;H04L7/033;H04L7/04;H04L7/08 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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