发明名称 |
Triple data system for high data rate communication systems |
摘要 |
A slot-aligned IQ data buffer scheme has a third buffer that allows a processing engine to slide the selection of a vector to be processed so that it aligns with the framing of the data. This is particularly advantageous for CDMA and WCDMA systems where there are overlaying coded data streams, each with its own frame timing, since data is processed cleanly at boundaries in the data such that the processing hardware can be minimized. A first level of muxing selects a pair of buffers having the data to be processed from among three buffers. A second level of muxing selects the sample number required. The third level of muxing selects the correct chips for the alignment of the slot. The third stage is implemented with a barrel shifter to minimize hardware generally associated with use of multiplexing.
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申请公布号 |
US6721295(B1) |
申请公布日期 |
2004.04.13 |
申请号 |
US20000648184 |
申请日期 |
2000.08.25 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
BROWN KATHERINE G. |
分类号 |
H04B7/26;(IPC1-7):H04B7/216 |
主分类号 |
H04B7/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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