| 摘要 |
PROBLEM TO BE SOLVED: To compensate for the lack of a clock signal generated, when there is a difference between the oscillation frequency of a ring oscillation circuit and a bit rate of a received signal. SOLUTION: A signal from a NAND output terminal 7 of an AND circuit 3 in a first stage is divided into two and provides k (k is an integer≥1) periods of the clock signal of the delay difference between the divided outputs by delay elements 26, 27 for connecting to input terminals 21, 22 of an AND circuit 25 in a second stage. A delay which makes the loop delay (n + 1/2) periods (n is an integer≥0) of the clock signal is given to a path, from a signal input terminal 1 to an input terminal 5 of an AND circuit 3 in the first stage, and an AND output terminal 23 of the AND circuit 25 in the second stage is connected to the input terminal 5 in the first stage. A clock signal is extracted from a clock output terminal 2. COPYRIGHT: (C)2004,JPO
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