发明名称 RESET METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To suppress power consumption in performing reset by being synchronized with a clock signal. <P>SOLUTION: This reset method of a semiconductor integrated circuit device has a plurality of circuit blocks. The method is provided with a step for supplying reset signals to the plurality of circuit blocks, a step for generating block clock signals to each of the plurality of circuit blocks based on the clock signals for prescribed period for each according to the reset signals and a step for resetting the circuit blocks corresponding to the block clock signals by using the block clock signals according to the reset signals. <P>COPYRIGHT: (C)2004,JPO</p>
申请公布号 JP2004110718(A) 申请公布日期 2004.04.08
申请号 JP20020275798 申请日期 2002.09.20
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MINEMARU TAKAYUKI
分类号 G06F1/24;G06F1/04;H03K17/22;(IPC1-7):G06F1/24 主分类号 G06F1/24
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