| 摘要 |
A power supply rejection circuit and method thereof for capacitively-stored reference voltages is disclosed. The power supply rejection circuit generally comprises a comparison circuit for comparing a signal associated with a power supply such as, for example, a Wheatstone bridge configuration, to a stored reference voltage, such that the comparison circuit includes at least one existing capacitor therein. At least one additional capacitor can be then coupled to the comparison circuit, such that the additional capacitor creates a capacitively-coupled voltage divider. This capacitively-coupled voltage divider negates the first order effects of power supply noise in the system. This effect significantly reduces the effect of power supply noise and improves signal jitter associated with the comparison circuit during a comparison of the signal to the stored reference voltage utilizing the comparison circuit.
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