| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce chip area by decreasing the number of sense amplifiers SA in a whole semiconductor memory device. <P>SOLUTION: Memory cells are arranged respectively at intersection positions of word lines and the first bit lines 1BL formed in each cell array block B0∼B7. The plurality of first bit lines 1BL are connected selectively to the second bit lines 2BL1 and 2BL2 through a bit line selector 200. These second bit lines 2BL1 and 2BL2 are formed over a plurality of cell array blocks, and they are connected respectively to one sense amplifier SA. Thereby, access for a memory cell MC in a plurality of cell array blocks can be performed by one sense amplifier SA. <P>COPYRIGHT: (C)2004,JPO |
