发明名称 |
Method of reducing voiding in copper interconnects with copper alloys in the seed layer |
摘要 |
A method for forming a copper interconnect with improved via integrity and elimination of via voiding employs a copper seed layer having an alloy element within the seed layer. The alloy element increases the resistance of the copper seed layer to acidic plating chemistry as the vias are filled and as the pulse-reverse wave form is initiated in the electrochemical plating process. The prevention of void formations at the bottom of the via improves the copper filling, with resulting improved electromigration performance, reduced via resistance and improved product speed.
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申请公布号 |
US2004061237(A1) |
申请公布日期 |
2004.04.01 |
申请号 |
US20020254540 |
申请日期 |
2002.09.26 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
ZHAO LARRY;BESSER PAUL R.;WANG CONNIE |
分类号 |
H01L21/288;H01L21/768;(IPC1-7):H01L23/52 |
主分类号 |
H01L21/288 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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