发明名称 Dram core refresh with reduced spike current
摘要 A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge currents during a refresh operation, as compared to normal memory access. Unlike normal memory accesses, data is not needed, and a fast access time is not required. This allows the current to be spread using different circuitry for driving the current to lessen current spikes. The spread current is still maintained within the timing of a normal memory access.
申请公布号 US2004062120(A1) 申请公布日期 2004.04.01
申请号 US20030625914 申请日期 2003.07.22
申请人 发明人 TSERN ELY K.;BARTH RICHARD M.;DAVIS PAUL G.;HAMPEL CRAIG E.
分类号 G11C8/08;G11C11/406;G11C11/408;(IPC1-7):G11C7/00 主分类号 G11C8/08
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