| 摘要 |
PROBLEM TO BE SOLVED: To reduce power consumption when a semiconductor memory operates while maintaining a high-speed operation without increasing the chip size. SOLUTION: A pulse generation circuit generates a column pulse of a plurality of times in response to a reading command. An address counter sequentially outputs addresses that follow an external address supplied in accordance with the reading command as an internal address. A column decoder synchronizes with a column pulse to sequentially select column selection lines. Data of a plurality of bits read out from a memory cell in response to the reading command of one time are sequentially transmitted to a common data bus line through a column switch. As a result, the number of data bus lines can be minimized to prevent increase in the chip size. Because the data of a plurality of bits can be transmitted by one data bus line, a memory area activated in response to the reading command can be minimized. As a result, it is possible to reduce power consumption. COPYRIGHT: (C)2004,JPO
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