发明名称 Method of fabricating a ferroelectric stacked memory cell
摘要 The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line. In this way, the manufacturing process is not critical and the size of the cells is minimal.
申请公布号 US2004058493(A1) 申请公布日期 2004.03.25
申请号 US20030621262 申请日期 2003.07.15
申请人 STMICROELECTRONICS S.R.I.;STMICROELECTRONICS S.A. 发明人 DEMANGE NICOLAS;ZAMBRANO RAFFAELE
分类号 H01L21/8242;H01L21/8246;H01L27/108;H01L27/115;(IPC1-7):H01L21/823;H01L21/824 主分类号 H01L21/8242
代理机构 代理人
主权项
地址