发明名称 Accelerated layout processing using OPC pre-processing
摘要 Performing optical proximity correction (OPC) is typically done during a critical time, wherein even small delays in finishing OPC can have significant adverse effects on product introduction and/or market exposure. In accordance with one feature of the invention, sets of repeating structures in library elements and/or layout data can be identified during a noncritical time, e.g. early in cell library development, possibly years prior to the direct application of OPC to a final layout. OPC can be performed on repeating structures during this noncritical time. Later, during the critical time (e.g. during tape out), an OPC tool can use the pre-processed structures in conjunction with a chip layout to more quickly generate a modified layout, thereby saving valuable time as a chip moves from design to production.
申请公布号 US2004060034(A1) 申请公布日期 2004.03.25
申请号 US20020253204 申请日期 2002.09.23
申请人 NUMERICAL TECHNOLOGIES, INC. 发明人 COTE MICHEL LUC;PIERRAT CHRISTOPHE;HURAT PHILIPPE
分类号 G03F1/14;G06F17/50;(IPC1-7):G06F17/50 主分类号 G03F1/14
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