| 摘要 |
Disclosed is an impedance comparison integrated circuit. The integrated circuit includes a current mirror part, a discharging part, a differential amplification part and a first output part. The current mirror part provides current to a first and second input terminal, respectively, during a first interval of every period. The discharging part provides a discharging path to the first and second input terminals, respectively, during a second interval of every period. The differential amplification part performs a differential amplification on signals input from the first and second input terminals, respectively, during the first interval of every period. The first output part outputs a first output signal to the first output terminal in response to the differential amplification part. Accordingly, parasitic impedance difference between each parasitic impedance of the first and second input terminals is minimized, and input offset error is reduced, so that impedance sensing with high precision is possible.
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