FIELD PROGRAMMABLE GATE ARRAY

摘要

PROBLEM TO BE SOLVED: To provide a field programmable gate array (FPGA) which can shorten a configuration time and a time for rewriting wiring information and logic arrangement information, and can reduce its occupation area. SOLUTION: For storing FPGA wiring information, magnetic memory elements MTJ1 to MTJn are provided as MRAM memory cells. A shift register 71 is used to input the wiring information to the magnetic memory elements MTJ1 to MTJn. The register 71 includes register elements SR1 to SRn corresponding to the magnetic memory elements MTJ1 to MTJn. The wiring information are serially input to the register elements SR1 to SRn and stored therein. When the power is turned on, the wiring information of the magnetic memory elements MTJ1 to MTJn are latched by latch elements LT1 to LTn and output to a switch circuit 6 for interconnecting logic blocks. COPYRIGHT: (C)2004,JPO