| 摘要 |
<p>Method of manufacturing a semiconductor device comprising a semiconductor body ( 1 ) which is provided at a surface ( 2 ) with a non-volatile memory comprising a memory cell with a gate structure ( 4 ) with an access gate ( 19 ) and a gate structure ( 3 ) with a control gate ( 5 ) and a charge storage region situated between the control gate ( 5 ) and the semiconductor body ( 1 ), such as a floating gate ( 6 ). In this method on the surface ( 2 ) of the semiconductor body ( 1 ) a first one of said gate structures is formed with side walls ( 10 ) extending substantially perpendicular to the surface, a conductive layer is deposited ( 13 ) on and next to said first gate-structure, the conductive layer is subjected to a planarizing treatment until the first gate structure is exposed and the so planarized conductive layer is patterned so as to form at least a part of the other gate structure adjoining the first gate structure. Said patterning of the planarized conductive layer is performed in that the planarized conductive layer ( 14 ) is etched back so as to expose an upper portion ( 15 ) of the side walls of the first gate structure, a spacer ( 18 ) is formed on the exposed upper portion ( 15 ) of the side walls of first gate structure and the conductive layer ( 16 ) is etched anisotropically using the spacer as a mask. Thus very small memory cells can be realized.</p> |
