SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, DELTA-SIGMA MODULATION TYPE FRACTIONAL DIVISION PLL FREQUENCY SYNTHESIZER, RADIO COMMUNICATION DEVICE, DELTA-SIGMA MODULATION TYPE D/A CONVERTER

摘要

A fractional divider (28) includes a latch (31) for holding division data, a DeltaSigma modulator (33), a digital dither circuit (32) for receiving a digital input F representing the fractional portion of the division data from the latch (31) and supplying a digital output alternately changing between F+k and F-k (k is an integer) or the F value itself to the DeltaSigma modulator (33), and circuit means (34 to 38) for executing fractional division operation according to the integer portion (M value) of the division data and the output of the DeltaSigma modulator (33). The digital dither circuit (32) serves to suppress a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the DeltaSigma modulator (33) has received a particular F value (for example F = 2<n-1>).