| 摘要 |
PROBLEM TO BE SOLVED: To retrieve all defective memory cell information necessary for analysis afterward even if a built-in memory is tested at actually specified speed by using a BIST technique. SOLUTION: Read data of a memory cell 3 to be tested are compared with output data of an expected value generating circuit 4 in an expected value comparison circuit 5. If discordance is detected in the expected value comparison circuit 5, test interruption is minimized by storing in a defective memory cell information accumulating memory 11 a test item held in a test item detecting circuit 7, address information of the memory cell held in an address register 8, and bit position information held in a defective bit detecting circuit 9, and the built-in memory is tested at actually specified speed. The defective memory cell information accumulated in a defective memory cell information accumulating memory 11 is read at low speed after the completion of the test. COPYRIGHT: (C)2004,JPO
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