发明名称 Integrated circuit, integrated circuit design method and hardware description generation method to generate hardware behavior description of integrated circuit
摘要 A functional block for verifying correct interface operation of any functional block is generated from interface description and installed on a LSI chip. To accomplish this, from the interface description, hardware description of a synthesizable interface checker is generated. Means for selecting interface functions to be checked is provided, thereby making it possible to reduce the overhead of circuits to be installed on the LSI.
申请公布号 US6708322(B2) 申请公布日期 2004.03.16
申请号 US20020083341 申请日期 2002.02.27
申请人 HITACHI, LTD. 发明人 ITO MASAKI
分类号 G06F11/25;G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G06F17/50 主分类号 G06F11/25
代理机构 代理人
主权项
地址