发明名称 |
Sigma-delta pulse-width-modulated signal generator circuit |
摘要 |
A circuit for generating a pulse-width-modulated signal comprises a phase-locked loop (PLL) having a duty-cycle-insensitive phase comparator and a Sigma-Delta pulse width modulation circuit suitable for providing the voltage-controlled oscillator function of the PLL. Thereby, frequency of the signal generated is synchronized by the PLL to the specified frequency of a synchronization signal, and is thus independent of the duty cycle.
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申请公布号 |
US6707408(B2) |
申请公布日期 |
2004.03.16 |
申请号 |
US20020232954 |
申请日期 |
2002.08.29 |
申请人 |
STMICROELECTRONICS S.A. |
发明人 |
GUEDON YANNICK;MAIGE PHILIPPE |
分类号 |
H03K5/26;H03K7/08;H03L7/099;(IPC1-7):H03M3/00 |
主分类号 |
H03K5/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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