| 摘要 |
When data is read from one of the memory elements in a memory cell [i] in a reverse read mode, a word line WL1 is set at a supply voltage Vdd, a control gate CG [i+1] is set at 1.5V, and a control gate CG [i] is set at an override voltage (for example, 3V). When a bit line BL [I+1] is 0V and a bit line BL [i] is connected to a sense amplifier, the gate voltage BS0 of a bit line selection transistor located midway of the bit line BL [i] is set at a high voltage (for example, 4.5V), in order to ensure current which flows through the bit line BL [i] connected to the drain of the memory cell [i]. Since the voltage of the bit line BL [i+1] connected to the source of the memory cell [i] becomes a value close to 0V (on the order of several tens to hundred mV), the back gate of a bit line selection transistor exerts little influence, and hence, the gate voltage BS1 of this bit line selection transistor is set at the supply voltage Vdd.
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