| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide constitution of peripheral circuits suitable for a high speed parallel input/output operation of multi-bits data in a nonvolatile storage device provided with a memory cell of which the electric resistance is varied in nonvolatile fashion in accordance with the level of storage data written by a data writing current. <P>SOLUTION: A peripheral circuit 10 writes and reads input data DIN and output data DOUT of L bits (L:integer of 2 or more) inputted/outputted to/from a data node 10# for memory cell blocks 5a, 5b being selectively an object of access. The peripheral circuit 10 divides each of data writing operation and data reading operation into a plurality of stages by using circuit groups 20a, 20b, 25a, 25b, 30, 40, 50, 60 and 70 operated in response to to a clock signal CLK, and performs pipeline processing. <P>COPYRIGHT: (C)2004,JPO</p> |
