| 摘要 |
PURPOSE: To solve a problem in which a phase error(jitter) normally becomes large since intervals of phase comparison become long when the transition rate of input data is low or when an internal clock is generated by multiplying an external clock at a high multiplication rate. CONSTITUTION: A clock generator comprises a first phase comparator 1 which makes a phase comparison between an externally supplied reference signal DATA, CLK1 and the internal clock CLK2, a phase synchronous clock generating circuit 6 which generates a clock CLK3 for comparison phase synchronizing with the reference signal and having a higher clock transition rate than the reference signal, a second phase comparator 7 which makes a phase comparison between the clock for comparison and internal clock, an adder 4 which adds together first phase difference information obtained by the first phase comparator and second phase difference information obtained by the second phase comparator, and an internal clock generating circuit 5 which generates the internal clock phase adjusted according to the output of the adder.
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