| 摘要 |
A level shifter (3) includes first and second P type TFTs (5, 6) and first and second N type TFTs (7, 8) for latching levels of first and second output nodes (N5, N6), third and fourth N type TFTs (9, 10) for setting levels of the first and second output nodes (N5, N6), and first and second resistance elements (11, 12) and first and second capacitors (13, 14) for applying between gate-source of the third and fourth N type TFTs (9, 10) a voltage (about 6V) higher than an amplitude voltage (3V) of an input signal (VI) in response to rising and falling edges of the input signal (VI), respectively.
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