| 摘要 |
A ferroelectric memory device of the present invention comprises: a main bitline pull-up controller for pulling up a main bitline to a positive voltage; a column selection controller for connecting the main bitline to a data bus by a column selection control signal; a cell array connected between the main bitline pull-up controller and the column selection controller; and a driving voltage booster for comparing a predetermined threshold voltage with a detected power voltage and regulating an output level of the driving voltage according to comparison result. The ferroelectric memory device of the present invention also comprises bitlines divided into a main bitline and a plurality of sub-bitlines connected to the main bitline. When a specific cell is approached, a sub-bitline connected to the corresponding to the cell is just connected to the main bitline, thereby reducing the driving load of the bitline to the load of the sub-bitline.
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