| 摘要 |
An interface circuit for interfacing one or more compute nodes to a mesh is capable of serving a wide range of MPP systems. The interface circuit includes a first bus interface for interfacing with a first bus, a second bus interface for interfacing with a second bus, and a mesh interface. Control logic is coupled to the first bus interface, the second bus interface, and the mesh interface. The control logic includes circuitry for placing the interface circuit in a first mode in which a compute node resides on the first bus and a second mode in which the compute node resides on the second bus. The first bus may be a split-envelope bus such as the MIPS avalanche bus. The second bus may be a single-envelope bus such as the PCI bus.
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