| 摘要 |
PROBLEM TO BE SOLVED: To provide a data processor capable of preferentially starting an interrupt process if an interrupt request occurs in the middle of burst transfer into a cache memory. SOLUTION: If the occurrence of an interrupt request IR is detected in the middle of burst transfer into an instruction cache 3, the instruction cache 3 interrupts the burst transfer and creates interrupt information 35. When the interrupt process is complete and the original program is recovered, the instruction cache 3 resumes the burst transfer from the interrupted portion by referring to a resume address described in the address description part 35a of the interrupt information 35. COPYRIGHT: (C)2004,JPO
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