发明名称 |
Memory cell with vertical transistor and trench capacitor |
摘要 |
A memory cell with a vertical transistor and a trench capacitor. The memory cell includes a substrate having a trench and a trench capacitor disposed in the lower trench. A control gate, with a p-type polysilicon germanium layer and an overlying p-type polysilicon layer, is disposed in the upper trench and insulated from the substrate. A first insulating layer is disposed between the trench capacitor and the control gate. A first doped region is formed in the substrate around the first insulating layer and a second doped region is formed in the substrate around the second conductive layer.
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申请公布号 |
US6696717(B2) |
申请公布日期 |
2004.02.24 |
申请号 |
US20020299431 |
申请日期 |
2002.11.18 |
申请人 |
NANYA TECHNOLOGY CORPORATION |
发明人 |
CHANG MING CHENG;LIN JENG-PING |
分类号 |
H01L21/8242;(IPC1-7):H01L29/72 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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