发明名称 Simulation method and simulation system of instruction scheduling
摘要 There is provided a simulation method of instruction scheduling comprising detecting a loop from an instruction sequence to be simulated, registering an instruction scheduling target instruction sequence in a loop detection state, comparing a current scheduling target instruction sequence with the registered scheduling target instruction sequence for each loop cycle, and skipping, when the current scheduling target instruction sequence matches the registered scheduling target instruction sequence, scheduling of that scheduling target instruction sequence, and newly registering, when the two instruction sequences do not match, the current scheduling target instruction sequence and executing scheduling.
申请公布号 US2004034852(A1) 申请公布日期 2004.02.19
申请号 US20030405944 申请日期 2003.03.31
申请人 SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER 发明人 NAKASHIMA HIROSHI
分类号 G06F11/28;G06F9/45;G06F9/455;(IPC1-7):G06F9/45;G06F9/44 主分类号 G06F11/28
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