| 摘要 |
A high-speed differential sampling flip-flop includes a differential data input, a differential offset control input, a sampling clock input, an output, a sampling latch, and an RS latch. The sampling latch includes a sampling latch reset circuit, a current steering circuit, first and second switches, and a regenerative latch. The sampling latch reset circuit is coupled to a first power supply and the current steering circuit. The current steering circuit has first and second control terminals which are coupled to the differential data input. The first switch is coupled between the current steering circuit and a second power supply. The regenerative latch is coupled to the current steering circuit, the second switch, and a third power supply. The sampling latch also includes first and second offset control current sources coupled to the current steering circuit and the second power supply, and having first and second control terminals coupled to the differential offset control input. The RS latch includes two cross-coupled nand gates and is coupled to the sampling latch and the output. On a transition of the sampling clock input from logic low to logic high, the differential data input is sampled, amplified to a low or high logic level, and transferred to the output. The differential offset control input is used to control the input offset of the sampling flip-flop.
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