Circuit for regenerating clock signals especially in high frequency cmos has offset compensation circuit to equalize output signals

摘要

A circuit for regenerating clock signals comprises an input differential amplifier (1) producing two signals (Bp,Bn) in response to two differential input clock signals (Ap,An) and two inverters (In1,In2) giving differential output signals (Ep,En). An offset compensation circuit adjusts the difference to zero or a constant value. An Independent claim is also included for a regenerating circuit as above not having an offset compensation circuit.