发明名称 FAULT TOLERANT COMPUTER SYSTEM, ITS RESYNCHRONIZATION METHOD, AND RESYNCHRONIZATION PROGRAM
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a fault tolerant computer system that significantly reduces the suspension period of system operation, and its resynchronization method. <P>SOLUTION: The fault tolerant computer system is a lock-step type system having a plurality of computing modules 100, 200 each having processors and memories, with the computing modules processing the same instruction sequence in clock synchronization. When a mismatch in the state of access to an external bus is detected between the processors within each of the computing modules 100, 200 and no fault of the entire system including the computing modules 100, 200 is detected, interrupts are generated to all the processors, and after delay adjustments are made to establish a match between the computing modules in the state of instruction execution, the process of resuming the operation of the computing modules in clock synchronization is performed. <P>COPYRIGHT: (C)2004,JPO</p>
申请公布号 JP2004046599(A) 申请公布日期 2004.02.12
申请号 JP20020204167 申请日期 2002.07.12
申请人 NEC CORP 发明人 YAMAZAKI SHIGEO;AINO SHIGEYUKI
分类号 G06F11/18;G01R31/317;G01R31/3185;G06F1/12;G06F11/00;G06F11/10;G06F11/16;G06F11/20;G06F11/273;G06F12/08;G06F12/14;G06F12/16;G06F13/00;(IPC1-7):G06F11/18;G06F15/177;G06F15/16 主分类号 G06F11/18
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