| 摘要 |
A shared bus multiprocessor system is provided. The system comprises a communications bus, a first processor, a second processor, and a clock. The first processor has a first output buffer that has a first output delay time. The second processor has a second output buffer that has a second output delay time. The second output delay time is less than the first output delay time. Finally, the clock provides a clock signal to the first and second processors, with the clock signal arriving at the second processor before the first processor.
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