| 摘要 |
The present invention is to provide an integrated circuit, a macrocell and method of layout for an integrated circuit capable of reduction in chip area using an area in macrocells. The macrocell according to the invention has concavity-shaped, and an integration circuit of the present invention includes a concave macrocell. The layout method according to this invention comprises, inputting a target macrocell, searching for blank areas in the macrocell, replacing the macrocell with a macrocell that the blank area searched is removed; and layout the integrated circuit using the macrocell that the blank area searched is removed. A macrocell excluding the non-circuit areas be used efficiently so that reduction in chip area can be realized by using the integrated circuit including the macrocell according to this invention.
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