发明名称 VARIABLE DELAY CIRCUIT AND PLL-FM MODULATION CIRCUIT USING THE SAME
摘要 <p><P>PROBLEM TO BE SOLVED: To improve the signal-to-noise characteristics and distortion characteristic of a frequency modulated wave. <P>SOLUTION: A frequency divider 28 divides the frequency of an output signal of a voltage controlled oscillator 30, an integrating circuit 29 integrates a modulated signal, a reference frequency divider 24 divides the frequency of a reference clock 23, and a variable delay circuit 25 is then used to apply phase modulation to the reference clock 23 by using an output signal of the integrating circuit 29. A phase comparator 26 compares the phase of an output signal of the frequency divider 28 with that of an output signal of the variable delay circuit 25, a loop filter 27 extracts the low-pass components of the output signal of the phase comparator 26 and gives the low-pass components as a frequency controlled voltage to the voltage controlled oscillator 30. The variable delay circuit 25 comprises a differential transistor in which a current source is connected to the collector side and the emitter side, capacitors connected to the collector of the differential transistor, and a current source with a switch for limiting the upper limit value and lower limit value of the voltage of the collector of the differential transistor to a predetermined value. <P>COPYRIGHT: (C)2004,JPO</p>
申请公布号 JP2004040593(A) 申请公布日期 2004.02.05
申请号 JP20020196654 申请日期 2002.07.05
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YANAI HIDEO
分类号 H03C3/00;H03H11/26;H03K5/13;(IPC1-7):H03H11/26 主分类号 H03C3/00
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