| 摘要 |
PROBLEM TO BE SOLVED: To efficiently and appropriately adjust timing of a complicated circuit. SOLUTION: This timing adjusting method is for a digital circuit formed by connecting a plurality of memory elements, which are synchronously operated with a clock, to each other via an intermediate combinational circuit. This method is provided with a step S1 of finding a pass hold violation value Th and a setup allowance Ts till becoming the setup violation for every passes interposed between the memory elements, a step S2 extracting the minimum setup allowance Tsm in the passes passing through the terminal for every input/output terminals of the memory elements and logic gates interposed in the violation pass causing the hold violation, and a step S3 preferentially determining the input/output terminal corresponding to the maximum setup allowance Tsm (max) in the respective minimum setup allowances extracted for every input/out terminals as a violation measures application part. COPYRIGHT: (C)2004,JPO
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