HIGH SPEED MULTIPLEXER CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a high speed multiplexer circuit that facilitates circuit integration by reducing the number of logic gates and simplifying a phase relation between data and a clock and wiring installed for a high speed clock in order to solve problems of high speed multiplexer circuits of prior arts having been so far reported which have many numbers of logic gates resulting in making the phase design between data sequences and clocks complicated and needing many logic gates that require high speed clocks. SOLUTION: The high speed multiplexer circuit is provided with: a plurality of input terminals to receive a plurality (2n) of input data signals (bit rate: f bps) to be multiplexed; a frequency divider that receives a clock signal whose frequency is 2n-1f(Hz)(n is an integer of 2 or over) and generates 2n-1kinds of clock signals with the same frequency whose phases, started from 0 degree, are deviated by 180×(1/2n-1)(degrees); 2nsets of flip-flop circuits for outputting data signals synchronously with any of outputs of the frequency divider; and a selector for receiving and multiplexing outputs of the flip-flop circuits and providing a data output whose bit rate is 2nf(bps). COPYRIGHT: (C)2004,JPO