SEMICONDUCTOR MEMORY DEVICE HAVING TEST MODE

摘要

PURPOSE: A semiconductor memory device having a test mode is provided to check a race margin between two signals during test and analysis by generating a column selection line enable signal and the first read pulse using different clocks. CONSTITUTION: According to the semiconductor memory device having a test mode, a clock generator(30) generates a clock signal(CLK), and a clock delay part(32) outputs a clock signal(CLK1) delayed by one clock by receiving the above clock signal generated from the clock generator. A CSL generator(34) generates a CSL enable signal by receiving the clock signal generated from the clock generator. A FRP generator(36) generates a FRP by receiving the delayed clock signal from the clock delay part. A SRP(Second Read Pulse) generator(38) generates a SRP signal by receiving the converted clock signal from the clock delay part. The first switch(42) transfers data read from the memory cell by the CSL enable signal. The first stage(44) stores data being output from the memory cell when the first switch is on. The second switch(46) transfers data read from the first stage by the above FRP.