| 摘要 |
PROBLEM TO BE SOLVED: To provide a large capacity burst transfer memory in which reduction in the chip area and high speed operations are simultaneously realized. SOLUTION: The memory is provided with a first memory having cell arrays arranged in a matrix manner, a second memory which has cell arrays arranged in a matrix manner and conducts random access operations faster than the first memory, and an interface circuit which controls the first and the second memories as one burst transfer memory. The circuit provides the burst transfer memory by assigning the addresses of the first and the second memories as continuous addresses, starting first random accesses of the first and the second memories at the times which are close to each other, making accesses to the second memory until the word lines of the first memory are activated and making continuous page accesses to the first memory after the word lines of the first memory are activated. COPYRIGHT: (C)2004,JPO
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