| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a solving method for reducing conductor paths by improving array density without reducing the dimension of a cell, and sharing a common path by two pairs of cells. <P>SOLUTION: A memory cell array(100) having a parallel memory planes is developed. Each memory plane includes the first resistance intersection plane of a memory cell (108a), the second resistance intersection plane of a memory cell (108b), a plurality of conductive word lines (102) shared between the first plane and the second plane of the memory cells, a plurality of bit lines (104) connecting one or more memory cells in the first plane to another memory cell in the second plane, and a plurality of uni-directional elements (110). Furthermore, it is possible to provide the uni-directional conductive path formed from the memory cell in the first plane to the memory cell in the second plane sharing the same bit line. <P>COPYRIGHT: (C)2004,JPO |
