| 摘要 |
A method and apparatus for design validation of complex IC with use of a combination of an event tester and a field programmable gate array (FPGA) or an emulator board. The design validation method eliminates logic simulation which is a bottleneck in design validation today. Because of the elimination of slow simulation from the design validation flow, extensive design validation can be done before design is taped-out for manufacturing, and because extensive design validation become possible, it eliminates the need of a prototype before mass production.
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