发明名称 Method for creating standard VHDL test environments
摘要 A method, a data structure, a computer program product and a computer for testing digital designs defining integrated circuits in a HDL before actually building the integrated circuits and, more specifically, for creating standard test environments for digital designs. One embodiment provides a method of creating an entity description for use in an automated testing environment, the entity description defining an entity of an integrated circuit in a hardware description language, the entity of the integrated circuit comprising at least one interface having a plurality of ports each associated with a pre-determined function. The method comprises, for at least one port of the plurality of ports, associating at least one indication of a specific procedure call with the at least one port, the specific procedure call defining the pre-determined function of the at least one port.
申请公布号 US2004015792(A1) 申请公布日期 2004.01.22
申请号 US20020196670 申请日期 2002.07.16
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 KUBISTA PAUL B.
分类号 G01R31/3183;G06F17/50;(IPC1-7):G06F17/50 主分类号 G01R31/3183
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