发明名称 SYSTEM AND METHOD FOR PROVIDING NETWORK TIMING RECOVERY
摘要 <p>A method and system for network timing recovery that recovers the timing reference by multiplying an 8kHz reference clock up to one of a number of higher frequencies whilst maintaining phase alignment. Further, the present invention allows the 8kHz reference signal to be generated from a software controlled frequency generator where no external reference is available. It also provides a configuration whereby the choice of external or internal 8kHz reference is controlled by software, and further than said 8kHz reference is always used as the input to the phase locked loop (PLL) clock multiplier. An algorithm to control the internal 8kHz generator will not require to take into account "phase jumps" where the frequency suddenly changes by a large amount by passing the generated 8kHz clock through the phase locked loop (PLL), where any large phase increase or decrease on the input clock will be filtered out and not passed though directly to the multiplied clock output.</p>
申请公布号 WO2004006478(A1) 申请公布日期 2004.01.15
申请号 WO2003US21355 申请日期 2003.07.08
申请人 GLOBESPANVIRATA INCORPORATED 发明人 JULYAN, JAYSON, BERNARD, ETHERIDGE
分类号 H03L7/099;H04J3/06;(IPC1-7):H04J3/06 主分类号 H03L7/099
代理机构 代理人
主权项
地址
您可能感兴趣的专利