| 摘要 |
With plesiochronous data communication, as in particular S(H)DSL transmission, data symbols (2) are transmitted at a constant symbol frequency in frames (1) with a time duration variable within limits. The length of the frames (1) is varied by inserting or omitting stuffing data symbols in relation to a nominal length, so that it is averaged over several frames (1) synchronously with a data clock. If the data clock frequency is synchronous with the symbol frequency, alternating stuffing data symbols are injected or omitted in the frames (1), so that the phase of the frames (1) varies constantly during the transmission. This variation however occurs at a high frequency and can be easily suppressed on the receiving side when recovering the data clock by means of a PLL. In the event of slight deviation in the synchronization between symbol frequency and data clock frequency, however to control the frame length in relatively long time intervals, stuffing data symbols must be injected or omitted several times one after the other, so that low-frequency jitter develops, which can no longer be suppressed by the PLL on the receiving side, if the jitter frequency is lower than the natural frequency of the PLL. According to the invention on the sending side the phase difference between the data clock and the clock of the frame transmission (7) is determined from in each case at least two successive frames (1), so that the influence of the alternating injection and omission of stuffing data symbols on the control system is eliminated. Additionally the control system is set up in such a manner that additionally to the alternating injection and omission of stuffing data symbols a large limit cycle arises, so that the phase difference additionally to the alternating stuffing executes a second limit cycle or a second operating movement in the control loop, which leads to a higher jitter frequency, which can be suppressed on the receiving side by the PLL.
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