发明名称 Clamp circuit
摘要 In the clamp circuit, the first transistor shifts a target clamp voltage by a gate-source voltage to output the target clamp voltage. The buffer circuit inputs the shifted voltage and output a reference voltage on the inputted shifted voltage. The gate of the second transistor is connected to the output terminal of the buffer circuit. The source of the second transistor is connected to the input terminal of the first transistor. In this structure, the reference voltage is supplied to the gate of the second transistor so that, when a terminal voltage of the input terminal of the IC is not less than a clamp voltage corresponding to the sum of the reference voltage and a threshold voltage of the second transistor, the second transistor turns on, whereby the terminal voltage is clamped to a clamp voltage related to the target clamp voltage.
申请公布号 US2004008070(A1) 申请公布日期 2004.01.15
申请号 US20030616426 申请日期 2003.07.09
申请人 ABE HIROFUMI;ISHIHARA HIDEAKI;NODA SHINICHI 发明人 ABE HIROFUMI;ISHIHARA HIDEAKI;NODA SHINICHI
分类号 H01L27/04;H01L21/822;H03K5/08;H04L25/02;H04L25/03;(IPC1-7):H03L5/00 主分类号 H01L27/04
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