| 摘要 |
<p>In one aspect, multiple blocks of intermediate representation (2a,2b) are permitted derived from a single portion of program code. Each of the multiple blocks represent the portion of program code under different entry conditions (e.g. for a different status of a processor register d0). In many cases only relatively few blocks (2a, 2b) will be required, and other potential variants of the portion of program code are never encountered. A second aspect of the invention applies to individual program code instructions (2) which have different effects or functions at different iterations. Corresponding special-case intermediate representation (2a,2b) is generated representing only the functionality of the instruction that is required at a particular iteration.</p> |
