发明名称 |
Device and method for selecting power down exit |
摘要 |
<p>A memory device includes a command decoder for generating a power-down signal in response to a power-down command, a mode register (MRS) for storing power-down exit information, a clock synchronization circuit such as a DLL or PLL circuit for generating an internal clock signal synchronized with an external clock signal, and a controller for controlling the DLL or PLL circuit. At power-down exit of the memory device, the power-down exit information can be selected between a fast wakeup time and a slow wakeup time.</p> |
申请公布号 |
EP1381053(A2) |
申请公布日期 |
2004.01.14 |
申请号 |
EP20030252365 |
申请日期 |
2003.04.14 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE, DONG-YANG;LEE, JUNG-BAE |
分类号 |
G06F1/04;G11C7/22;G11C5/14;G11C7/10;G11C8/00;G11C11/401;G11C11/407;G11C11/4074;(IPC1-7):G11C7/10 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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